1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit devices having series-connected field effect transistors (FETs) and, more specifically, to an integrated circuit device, such as a radio frequency (RF) switch, with series-connected fin-type field effect transistors (FINFETs) and integrated voltage equalization.
2. Description of the Related Art
Integrated circuit design decisions are often driven by device scalability and manufacturing efficiency.
For example, because size scaling of planar field effect transistors (FETs) resulted in reduced drive current as a function of reduced channel width, dual-gate FETs (also referred to herein as fin-type FETs or FINFETs) were developed to provide scaled devices with increased drive current and reduced short channel effects. Dual-gate FETs are non-planar FETs in which a fully depleted channel region is formed in the center of a relatively thin semiconductor fin with source and drain regions in the opposing ends of the fin adjacent to the channel region. A gate is formed over the top surface and on each side of the thin fin in an area corresponding to the channel region. A dielectric cap layer (such as a nitride cap layer) typically isolates the top surface of the channel region from the gate so that only two-dimensional field effects are exhibited. The effective channel width is determined by the fin height. Additionally, a fin thickness of approximately one-half (or less) the length of the gate can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. The effective channel width of dual-gate FETs and, thereby, the device drive current can be increased by incorporating multiple semiconductor fins.
Additionally, because size scaling of field effect transistors (FETs), including dual-gate FETs, has resulted in limits on the maximum source-to-drain voltage that any single FET can reliably switch, FET networks with multiple series-connected FETs (i.e., stacked FETs) were developed in order to support the switching of higher source-to-drain voltages. In such FET networks, the series-connected FETs are also often connected in parallel to a discrete voltage distribution network in order to ensure uniform voltage distribution and, thereby to avoid breakdown run-away, when the FETs are in the off-state, and have a large voltage across the entire series network of FETs.